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IDT5V41064
1 OUTPUT PCIE GEN1/2 SYNTHESIZER
IDT 1 OUTPUT PCIE GEN1/2 SYNTHESIZER
3
IDT5V41064
REV G 112111
Applications Information
External Components
A minimum number of external components are required for
proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01
μF should be connected
between VDD and the ground plane (pin 4) as close to the
VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into IDT pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal with
CL = 16 pF should be used. This crystal must have less than
300 ppm of error across temperature in order for the
IDT5V41064 to meet PCI Express specifications.
Crystal Capacitors
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
CL= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (CL- 8) * 2
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
Current Source (Iref) Reference Resistor - RR
If board target trace impedance (Z) is 50
Ω, then RR = 475Ω
(1%), providing IREF of 2.32 mA. The output current (IOH) is
equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41064 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the PCI-Express Layout Guidelines section.
The IDT5V41064 can also be terminated to LVDS
compatible voltage levels. See Layout Guidelines section.
Output Structures
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41064.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
R
R 475
6*IREF
=2.3 mA
IREF
See Layout
Guidelines
Ω
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